1. Field of the Invention
The invention relates to a method for fabricating a dielectric layer, and more particularly, to a method to fabricating capacitor dielectric layer.
2. Description of the Related Art
The factors to determine a capacitance of a capacitor includes the surface area of the electrode plates, the distance between the electrode plates, and the dielectric constant of the capacitor dielectric layer. Using a dielectric layer with a high dielectric constant can increase the amount of charges storage of a capacitor. However, a dielectric layer with a high dielectric constant also has effects on current leakage speed and breakdown voltage, so that this kind of materials are suitable for use upon application of low operation voltage.
A very common material used in a conventional dynamic random access memory includes a stack of an oxide layer, a nitride layer and another oxide layer. This is the so called ONO structure. The thickness of the middle nitride layer dominates over the overall thickness of the ONO structure. Therefore, the dielectric constant of ONO structure is basically determined by the dielectric constant of the nitride layer. However, the equivalent dielectric constant of the ONO structure is lower than that of a single nitride layer due to the existence of the oxide layers. Typically, in the ONO structure, the first oxide layer is a native oxide layer grown on a bottom electrode, whereas the second oxide layer is to provide a better surface on the nitride layer for the deposition of a top electrode.
The conventional method for forming ONO dielectric layer for a capacitor comprises a series of thermal treatments in different gas environment, so that a variety of furnace may be required. First of all, after the formation of a bottom electrode on a chip, the bottom electrode is in contact with air to form a native oxide layer which is difficult to be removed. The chip is then disposed into a fast thermal processing system with a rapidly raised temperature and an inflow of a mixture of ammonia (NH3) and dichlorosilane (SiH2Cl2). A nitride layer with a required thickness is thus formed on the native oxide layer.
The chip is then shifted into an atmospheric pressure furnace with moisture or wet oxygen. The furnace is heated up to 850 degree Celsius for about 15-30 minutes. An oxide layer is formed with a thickness thinner than that of the nitride layer since it is more difficult to oxidize the nitride surface. An ONO structure is thus formed.
In the above description, rapidly temperature raising furnace and atmospheric pressure furnace are required to form the ONO structure, and while transporting the chip from one furnace to another, contamination is inevitable. Furthermore, since a rapidly temperature raising furnace can contain less amounts of chips compared to the atmospheric pressure furnace, so the throughput is limited.
In the invention, an in situ process is adapted. That, different gases are infused into an identical reaction furnace at different steps, so that a nitride layer and an oxide layer is formed by a simplified process. Since the low pressure vertical furnace can contain a larger amount of chips compared to the conventional furnace, the throughput can be enhanced. Furthermore, there is a possibility for forming an oxynitride layer between the native oxide layer and the polysilicon bottom electrode. Therefore, the pinholes of the silicon nitride is filled to prevent leakage current and ion penetration.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.